As is known in the art, scaling traditional semiconductor field-effect transistors (FETs) like modulation-doped FETs (MODFETs) or high electron mobility transistors (HEMTs) having very short channel and gate length spacings in the sub-micron range below 0.1 um to maximize gain performance at microwave, millimeter and THz frequencies leads to significant large peak electric field under the gate electrode on the drain side that lowers breakdown voltages. This undesired tradeoff between frequency performance and device breakdown limits the transistor's overall RP power and efficiency performance.
In recent years, field plates are becoming a common addition to these transistors to reduce the peak electric field to enhance breakdown thus providing a means to alleviate the performance tradeoff just described. These field plates have taken on several forms as either a fourth electrode placed between the gate and drain or integrated as an extension of the gate electrode on the drain side or both. Typical dimensions of the field plates range depending on application from a few microns or tenths of microns to tens of microns. In this range, however additional parasitic capacitances are added that detrimentally impacts gain performance yielding little benefit for high frequency transistors.
One type of field plate structure is described in U.S. Pat. No. 7,662,698, entitled “Transistor having field plate”, inventor Tabatabaie, assigned to the same assignee as the present invention. Another type of field pate is formed by extending one side of the top of a mushroom shaped, sometimes referred as a T-shaped gate as shown in U.S. Published Patent Application Nos. U.S. 2008/0128752 and U.S. 2013/0252386. The above-described field plate structure is asymmetric in that the field, plate is extended over only one side of the gate. Another type of field plate is described in U.S. Pat. Nos. 7,750,370 and 7,897,446. As described therein an electron beam (e-beam) lithography (EBL) resist layer is formed on the source-drain metallizations and a protective dielectric layer. Electron Beam Lithography (EBL) is applied to the resist layer to fern a resist opening having a profile in which the width is comparatively narrow in a lower portion and comparatively greater in an upper portion. Alternatively, a self-supporting mask can be used with a flood electron gun source which provides a collimated beam of electrons. The mask can then be imaged directly on the resist layer to thereby form the window. Alternatively, electron beam lithography utilizing bi-layers of various resists can be used for the patterning process. A predetermined portion of the protective dielectric layer is completely or partially etched via the resist opening to form a window in the protective dielectric layer. An anisotropic dry etch is preferably used so that the resist layer and the predetermined portion of the protective dielectric layer are etched vertically while the lateral etch rates of both layers remain negligible. The final size of window is therefore very close to the original (pre-etch) size of the resist opening in its lower portion. The resist opening is widened so that a width of a lower portion of the resist is opening is greater than a width of the window in the protective dielectric layer. The widening can be achieved by performing a post-etch oxygen plasma etch on the resist opening so that only the resist opening is widened while a width of the window in the protective dielectric layer is not substantially effected. Widening the resist opening with respect to the window permits formation of miniature wings on both sides of the T-gate. The wing on the drain side of the gate can serve as a miniature gate-connected field mitigating plate. Here, the field plate is formed at the bottom of the stem of the T-shaped gate using e-beam lithography, which has well-known disadvantages of slow throughput and increased complexity making this approach expensive and less desirable for high yield/volume manufacture. Further, the method used to form the field plate results in a symmetrical field, plate that extends on both sides of the gate, which is unnecessary as the necessary electric field reduction for breakdown enhancement is only on the drain side of the gate. Having a field plate on the source side contributes additional gate-source parasitic capacitance thereby impacting gain performance.
Shrinking field plates into the nanometer scale dimensions reduce these parasitics while still providing the necessary field-reduction required to enhance device breakdown. However, their fabrication through traditional liftoff processes and lithographic techniques (e.g. optical or electron beam at the manufacturing scale with high reproducibility and yield are difficult given the small dimensions and critical placements involved.